1. Field of the Invention
The invention generally relates to semiconductor technologies, and more particularly to a mechanical stress diversion under bondpads on semiconductor chips.
2. Description of the Related Art
Conventional techniques for protecting structures on semiconductor chips include the approach described in U.S. Pat. No. 6,495,917 (hereinafter the '917 patent) issued to Ellis-Monaghan, et al. on Dec. 17, 2002, the complete disclosure of which is herein incorporated by referenced. As described in the '917 patent, the use of low dielectric potential (k) interlevel dielectric (ILD) materials (e.g., spin-on-glass (SOG), Hydrogensilsesquioxane (HSQ), Methylisilane (MSQ), Benzocyclobutene (BCB), etc.) has become very popular for input/output (I/O) and mechanical support structures which are applied to a previously fabricated semiconductor chip. Such I/O and support structures are formed after the logical function sections of the semiconductor chip have been completed. Therefore, such structures/processing are sometimes referred to as “back end of line” (BEOL) structures/processing because they are formed at the back end of the production line.
However, many low k materials are brittle or soft as compared to silicon dioxide and, when bonding forces are applied; the low k materials can be easily damaged. More specifically, the forces applied during bonding processes (such as ultrasonic wirebonding) or during the formation of solderball (C4) connections, can damage the low k dielectric materials. Thus, the damage from ultrasonic energy (wirebonding), capillary pressure and temperature can weaken or collapse the low k insulator. Furthermore, the mechanical stresses associated with structures below the chip bondpads are such that a significant build up of these stresses may result in material failure, fatigue, and eventual device breakdown. The stress and strain of a given material are directly proportional to one another and the proportionality in its simplest form is given by the relationship σ=Eε, where σ is the stress of the material, εis the strain of the material, and E is the modulus of elasticity of the material.
FIG. 1 illustrates a conventional semiconductor device with support structures. A bulk silicon substrate layer 1 is shown with an oxide layer 3 disposed thereon. Moreover, formed within the oxide layer 3 is a layered support structure 4 which is usually made from copper and is configured from the top of the silicon substrate layer 1 all the way up to the bottom of the bondpad 5. Such a configuration has been used to prevent failure of the oxide layer (fill material) 3.
The industry has long sought to incorporate protective structures over the semiconductor chip, or selective portions thereof, to minimize the impact of these forces on the chip structures. While the techniques described in the '917 patent are superior for the purposes for which it is designed; i.e., supporting structures to avoid failure in the fill material (low k material) during wirebonding, there remains a need to shield active chip devices from mechanical stresses, especially below the chip bondpads, where significant forces are applied resulting in increased mechanical stresses in those areas.